(a) Field of the Invention
The present invention relates to a liquid crystal display (LCD) and a method for driving the same. More specifically, the present invention relates to an LCD having its screen divided into two sections and driven individually, and a method for driving the same.
(b) Description of the Related Art
As personal computers and televisions become lighter in weight and thinner in profile, display devices must also become lighter in weight and thinner in profile. Accordingly, flat panel display devices such as LCDs are increasingly replacing the cathode ray tube (CRT).
In order to obtain desired image signals, the LCD applies an electric field to liquid crystal material having anisotropic dielectricity that is injected between two substrates, and controls the light amount permeating through the substrates by the intensity of the electric field. An LCD is one of the most commonly used portable flat panel display devices. In particular, a thin film transistor liquid crystal display (TFT-LCD), employing the TFT as a switching element, is widely used.
The LCD comprises a plurality of gate lines that transmit scanning signals. A plurality of data lines crossing the gate linestransmit image data. And a plurality of pixels formed by regions defined by the gate lines and data lines are interconnected through the gate lines, data lines and switching elements.
A method for applying the image data to each pixel in such an LCD will now be described.
When the scanning signals to turn on the gates (or gate-ON signals) are sequentially provided to the gate lines, the switching elements coupled to the gate lines are sequentially turned on. Image signals (i.e., data voltages) to be provided to pixel rows corresponding to the gate lines are concurrently provided to the respective data lines. The image signals provided to the data lines are then applied to the respective pixels through the switching elements that have been turned on. At this time, by sequentially applying the gate-ON signals to all the gate lines during one frame period such that the image signals are applied to all the pixel rows, one frame of image is displayed.
A recently developed higher-resolution LCD requires more gate lines. However, since the time for scanning a frame is limited to 1/60 of a second, the time interval of the gate-ON signal to be provided to the respective gate lines becomes shorter. Hence, it is difficult to provide sufficient image signals (i.e., the data voltages) to the image rows through the switching elements, which degrades the picture or image quality.
Therefore, a method has been disclosed recently to drive an LCD by dividing the display screen into two parts (an upper part and a lower part) in order to obtain a sufficient gate-ON time. Such a drive method is called a ‘dual scan method’.
FIG. 1 shows an LCD adopting a dual scan method.
As shown in the drawing, the LCD using the dual scan method comprises a liquid crystal display (LCD) panel 10, an upper data driver 21, a lower data driver 22, an upper gate driver 31 and a lower gate driver 32.
The LCD panel 10 comprises a plurality of gate lines G1, G2, . . . , Gm, Gm+1, . . . , G2m to transmit the gate-ON signals and a plurality of data lines D1, D2, . . . , Dn, C1, C2, . . . , Cn to transmit the data voltages (i.e., image signals). Regions defined by the crossing of the data lines and gate lines form pixels. Each pixel comprises a TFT 12, a gate electrode of which is coupled to a gate line and a source electrode of which is coupled to a data line, a pixel electrode 14 coupled to a drain electrode of the TFT 12 and a common electrode (not illustrated) to which a common voltage is supplied. The plurality of gate lines are divided into an upper gate line block and a lower gate line block, each comprised of m gate lines, respectively G1, G2, . . . , Gm, and then, Gm+1, . . . , G2m. The data lines D1, D2, . . . , Dn coupled to the pixels corresponding to the gate lines G1, G2, . . . , Gm of the upper gate line block are separated from the data lines C1, C2, . . . , Cn coupled to the pixels corresponding to the gate lines Gm+1, . . . , G2m of the lower gate line block. For example, an upper pixel of a first column is coupled to the data line D1 and a lower pixel of the first column is coupled to the data line C1.
The upper and lower gate drivers 31 and 32, coupled respectively to the upper and lower gate line blocks, sequentially provide gate-ON voltages to the gate lines of the upper and lower gate line blocks, respectively. At this time, the gate-ON voltages are provided to the gate lines from the first gate line and to the last gate line. The upper and lower data drivers 21 and 22, located respectively in the upper part and lower part of the LCD panel, supply the data voltages to the upper data lines D1, D2, . . . , Dn and the lower data lines C1, C2, . . . , Cn, respectively.
The operation of the LCD will be described hereinafter.
The gate-ON signals are sequentially provided to the TFTs 12 from the gate lines of the upper and lower gate line blocks starting from the first gate line then to subsequent gate lines. Concurrently, the data voltages (i.e., image signals) are provided to the upper and lower data lines. The TFTs 12 are turned on by the gate-ON signals, and the data voltages supplied to the data lines are provided to pixel electrodes through the TFTs 12 that are turned on. Electric fields generated by differences between the pixel voltages (i.e., the voltages supplied to the pixel electrodes) and the common voltages of the common electrodes are applied to the liquid crystal material. Since the arrangement of the liquid crystal material changes depending upon the intensity of the electric field (the intensity of the electric field varies according to the intensity of the data voltage), the amount of light permeating the liquid crystal material varies. Therefore, desired images are displayed on the LCD.
Since the gate-ON signals are concurrently supplied to the gate lines in the upper and lower gate line blocks, the above described dual scan type LCD has the advantage of a twice longer gate-ON time than the conventional single scan LCDs.
The electric field applied to the liquid crystal material continuously in the same direction deteriorates the liquid crystal material. Accordingly, when the data voltages are driven, the polarities of the data voltages are alternated between positive and negative values. Such a drive method is referred to as an inversion drive method.
Among different types of inversion drive methods are a frame inversion drive method that alternates the polarities every frame; a line inversion drive method that alternates the polarities every line; and a dot inversion drive method that alternates the polarities every pixel. The line inversion and dot inversion drive methods are most commonly used. However, the line inversion drive method or dot inversion drive method, when applied to the conventional dual scan type LCD, causes various drawbacks as described below.
It is assumed that the pixel of the LCD in FIG. 1 are driven by the dot inversion drive method, as shown by the positive (+) and negative (−) indications. The positive (+) polarity indicates that the polarity of the pixel voltage with respect to the common voltage is positive, and the negative (−) polarity indicates that the polarity of the pixel voltage with respect to the common voltage is negative.
A waveform of a voltage applied to the pixel electrode electrically coupled to the gate line Gm of the upper gate line block and to the data line D1, and a waveform of a voltage applied to the pixel electrode electrically coupled to the gate line Gm+1 of the lower gate line block and to the data line C1 are shown in FIG. 2.
As shown in FIG. 2 (a), in an ideal state, a voltage Vpu lower than the common voltage Vcom is uniformly applied during a period of one frame to the pixel electrode of the first pixel row coupled to the last gate line Gm in the upper gate line block. However, in the actual LCD, since a parasitic capacitance is generated between the pixel electrode and data line, the pixel voltage provided to the actual pixel electrode is affected by the voltage provided to the data line. That is, since the data voltages Vd1, the polarities of which with respect to the common voltage Vcom are periodically alternated are provided to the first data line D1 as shown in FIG. 2 (a), the actual voltage Va provided to the pixel electrode becomes the waveform as shown in FIG. 2 (b). For ease of explanation, the data voltages are assumed to be symmetrical with respect to the common voltage Vcom.
In more detail, as illustrated in FIGS. 2 (a) and (b), in the case where a pixel voltage Vpu with a negative polarity is provided and then a data voltage Vd with a positive polarity is provided to the data lines, the actual pixel voltage Va, unlike the ideal pixel voltage Vpu, is pulled in the direction of the common voltage by as much as ΔV due to the parasitic capacitance. On the other hand, if a data voltage with a negative polarity is provided to the data lines, the actual pixel voltage Va is pulled in the opposite direction of the common voltage by as much as ΔV.
As shown in FIG. 2 (c), in the ideal case, a constant voltage Vpd, higher than the common voltage Vcom, is provided to a pixel electrode of a first pixel row coupled to the first gate line Gm+1 in the lower gate line block during one frame interval. Further, a data voltage with a polarity identical to that of the data voltage provided to the data line D1 is supplied to a first data line C1. This is because the scanning process begins from the first gate line of each of the upper gate line block and the lower gate line block and the polarities of the pixel voltages coupled to the first gate line in the upper gate line block and lower gate line block are identical.
Therefore, because of the influence of the parasitic capacitance, the actual voltage provided to the pixel electrode has a waveform as shown in FIG. 2 (d). That is, as shown in FIGS. 2 (c) and (d), when the voltage Vpd with a positive polarity is provided and then the data voltage with a positive polarity is provided to the data lines, the actual pixel voltage Vb, unlike the ideal pixel voltage Vpd, is pulled in the opposite direction of the common voltage by as much as ΔV due to the parasitic capacitance. Also, if a data voltage with a negative polarity is provided to the data lines, the actual pixel voltage Vb is pulled in the direction of the common voltage by as much as ΔV.
As a result, since the voltages provided to the data lines influence the pixels of the two pixel rows on the boundaries in the opposite directions, the actual difference between the voltage provided to the pixels and the common voltage becomes the area marked by oblique lines in FIGS. 2 (b) and (d). This makes a bigdifference in the amounts of the light permeating the liquid crystal material in the pixels at the boundaries of the upper block and the lower block, which results in the inconsistent brightness on the boundaries. Eventually, this appears as undesired lines at the boundaries between the upper block and the lower block.